Conventionally, in semiconductor integrated circuits having high-speed transmission paths, multiphase clocks are widely used because they allow for a precise adjustment of a clock skew (a deviation of the timings when clocks reach nodes of a semiconductor integrated circuit; sometimes called a timing skew; hereinafter, it is referred to as the “skew”), compared to a single-phase clock Therefore, multiphase clocks have an important role in semiconductor integrated circuits having high-speed transmission paths.
As the semiconductor integrated circuit using multiphase clocks, typically, there are a scheme of generating multiphase clocks in a transmitter and transmitting the multiphase clocks to a receiver, and a scheme of generating multiphase clocks in a receiver based on a single-phase clock transmitted from a transmitter. In the former scheme, it is necessary to adjust a skew generated between the multiphase clocks having reached the receiver through high-speed transmission paths. In the latter scheme, it is necessary to use, as a frequency of the single-phase clock, a multiplied frequency of a frequency of the multiphase clocks. Conventionally, in the former scheme, it is very difficult to adjust such a skew generated between the multiphase clocks having reached the receiver, and therefore, the latter scheme has been generally used.
For example, Japanese Patent Publication No. H5-235923 discloses a phase adjustment circuit comprising a regenerating circuit and a differential delay circuit that receive a receiving signal, a timing extraction filter that receives an output of the differential delay circuit, and a phase-variable circuit that adjusts a phase of a clock signal that is output by the timing extraction filter. The phase adjustment circuit is used for adjusting the phase of the clock signal in an optical receiver configured such that a regeneration circuit latches a data signal in accordance with the clock signal output by the phase-variable circuit. The phase adjustment circuit further includes a first exclusive-or circuit that detects a phase difference between an input signal and an output signal of the regeneration circuit, a second exclusive-or circuit that receives an output of the differential delay circuit and an output of the first exclusive-or circuit, and a comparator that receives an output of the second exclusive-or circuit through a low-pass filter, and is configured to use, as a control signal for the phase-variable circuit, a signal that the comparator outputs with reference to a predetermined reference signal.
Further, for example, Japanese Patent Publication No. 2014-89664 discloses a skew adjustment circuit that adjusts a skew between clocks using an exclusive-or is disclosed. The skew adjustment circuit includes a first delay circuit that delays a first clock signal, a second delay circuit that delays a second clock signal having a different phase from the first clock signal, a third delay circuit that delays a third clock signal having a middle phase between the first clock signal and the second clock signal, a first logic gate that obtains the exclusive-or between an output of the first delay circuit and an output of the third delay circuit, a second logic gate that obtains the exclusive-or between an output of the second delay circuit and an output of the third delay circuit, and a feedback path that supplies, to the third delay circuit, a feedback voltage for adjusting delay time in the third delay circuit based on the difference between an output of the first logic gate and an output of the second logic gate.
Furthermore, for example, Japanese Patent Publication No. 2009-152682 discloses a phase difference smoother that reduces a phase error of multiphase clocks. The phase difference smoother includes phase filter circuits having weighting means for receiving multiple clocks that are of input multiphase clocks and that have a desired phase relation and performing a desired weighting for a phase of each clock and adding means for adding the weighted clocks, the number of which is equivalent to the number of the phases of the multiphase clocks, and outputs, as an output multiphase clock, a clock output from the phase filter circuit.